Exemplary embodiments relate to a semiconductor device and a method of manufacturing the same and, more particularly, to a 3-D non-volatile memory device and a method of manufacturing the same.
A non-volatile memory device retains data stored therein although a power supply is discontinued. Increasing the integration degree of memory devices having a 2-D structure which is fabricated in a single layer on a silicon substrate is reaching physical limits. Accordingly, a 3-D non-volatile memory device, in which memory cells are stacked vertically from a silicon substrate, is being developed.
Hereinafter, the structure of a conventional 3-D non-volatile memory device and features thereof are described with reference to relevant drawings.
FIG. 1 is a cross-sectional view of a conventional vertical channel-type non-volatile memory device.
As shown in FIG. 1, the conventional vertical channel-type non-volatile memory device includes a plurality of memory cells MC stacked along channels CH protruded from a substrate 10 including a source region S. Each of the memory cells MC includes the channel CH, a tunnel insulating layer, a charge trap layer, and a charge blocking layer 16 which surround the channel CH, and a gate electrode 15. Reference numeral ‘14’ denotes an interlayer dielectric layer.
The plurality of memory cells MC is coupled in series between a lower select transistor LST and an upper select transistor UST to form one string STRING. The lower select transistor LST and the upper select transistor UST include the channel CH, gate insulating layers 13 and 19 surrounding the channel, and gate electrodes 12 and 18. Reference numerals ‘11 and 17’ denote interlayer dielectric layers.
The channel of the upper select transistor UST of each of the strings STRING is coupled to a bit line BL.
In above-described vertical channel-type non-volatile memory device, the etch depth becomes deep according to an increase in the degree of integration of memory devices because the strings are arranged vertically from the substrate. Accordingly, there is a limit in increasing the degree of integration due to a limited etch process.
Furthermore, the vertical channel-type non-volatile memory device stores data using a charge trap type method of trapping electric charges in a deep level trap site within the charge trap layer. However, the charge trap type method has a slower erase speed than a floating gate type method of storing electric charges in the conduction band.
In particular, the vertical channel-type non-volatile memory device may not obtain a sufficient erase speed using, for example, only a method of discharging trapped charges when an erase operation is performed because the strings STRING are arranged vertically from the substrate. Accordingly, the trapped charge is to be discharged when the erase operation is performed and, at the same time, holes generated by Gate-Induced Drain Leakage (GIDL) are to be injected into the charge trap layer. In the conventional structure, however, the erase speed is slow and a probability that an erase error may occur is high because holes are not sufficiently generated by the GIDL.
FIGS. 2A and 2B are cross-sectional views of a conventional U-shaped channel-type non-volatile memory device. In particular, FIGS. 2A and 213 show an example in which the channel of a memory cell penetrates through a structure.
As shown, the conventional U-shaped channel-type non-volatile memory device is equipped with a plurality of memory cells MC stacked along the U-shaped channel. First and second select transistors ST1 and ST2 are provided at both ends of the U-shaped channel. Here, a string having the plurality of memory cells MC arranged in a U shape is formed between the first and the second select transistors ST1 and ST2. Furthermore, a bit line BL is coupled to the channel of the first select transistor ST1, and a source line SL is coupled to the channel of the second select transistor ST2.
The U-shaped channel includes a first channel CH1 buried in a pipe gate 20, a pair of second channels CH2 coupled to the first channel CH1, and a pair of third channels CH3 coupled to the second channels CH2, respectively. Each of the first channel CH1 and the second channels CH2 penetrates through a structure and has a hole at the center. An insulating layer 22 is buried in the central area. The third channel CH3 has a trench form or a burial form, which is described later.
Each of the memory cells MC includes a U-shaped channel, a tunnel insulating layer, a charge trap layer, and a charge blocking layer 21 which surround the U-shaped channel, and a gate electrode 24. Reference numeral ‘23’ denotes an interlayer dielectric layer.
The first and second select transistors ST1 and ST2 are formed at both ends of the U-shaped channel and configured to include the channels CH3 and the gate insulating layer 21 and the gate electrode 25 surrounding the channels CH3. The tunnel insulating layer, the charge trap layer, and the charge blocking layer 21 of the memory cell MC and the gate insulating layer 21 of the first and the second select transistors ST1 and ST2 are assigned a same reference numeral because they may be formed to have the same material by forming them at the same time.
Here, the memory device may have a different structure according to a form of the channels CH3 of the first and the second select transistors ST1 and ST2. FIG. 2A shows a partially trenched structure and shows an example in which the memory cell MC has the channel partially penetrating a structure, but the select transistors ST1 and ST2 have buried channels. That is, the select transistors ST1 and ST2 are fully buried with a channel layer including the central area of the channel CH3. FIG. 2B shows a fully trenched structure and shows an example in which the memory cells MC and the first and the second select transistors ST1 and ST2 have a channel that fully penetrates a structure. That is, the memory cells MC and the first and the second select transistors ST1 and ST2 have a fully trenched structure (that is, an empty space is formed vertically throughout a structure) in which the central area of the channels CH1, CH2, and CH3 is empty and the insulating layer 22 is formed to fill the empty area.
The U-shaped channel-type non-volatile memory device having the above structure may be higher in the degree of integration of memory devices than the vertical channel-type non-volatile memory device. However, as in the vertical channel-type non-volatile memory device, the U-shaped channel-type non-volatile memory device may not generate a sufficient amount of holes generated by GIDL. This is because the conditions of the generation of GIDL are not satisfied in view of the structural characteristic of the U-shaped channel-type non-volatile memory device. This is described in detail below.
First, in order to generate a sufficient amount of holes through GIDL, N type impurities of a high concentration are to be doped into the channels CH3 of the first and the second select transistors ST1 and ST2.
In the memory device having the structure shown in FIG. 2A, however, the channel that penetrates a structure is formed on the inner wall of a trench for the channel, and the channel CH3 doped with the N type impurities of a high concentration is formed. Accordingly, a native oxide layer is formed at the interface of the trench channel and the channel CH3, thereby degrading device characteristic. Furthermore, in the memory device having the structure shown in FIG. 2B, the areas of the channels CH3 of the first and the second select transistors ST1 and ST2 into which impurities will be doped are narrow because the channels CH3 have a trench shape. Accordingly, dope impurities of a high concentration may not be implanted, and thus a probability that an erase error may occur is high as compared with the memory device having the structure shown in FIG. 2A.
Second, after N type impurities of a high concentration are doped into the channels CH3 of the first and the second select transistors ST1 and ST2, a thermal treatment process is to be performed at 900° C. or higher in order to activate the N type impurities. In a structure having a high aspect ratio of a channel, such as the structures shown in FIGS. 2A and 2B, if the thermal treatment process is performed at 900° C. or higher, the components (that is, polysilicon) of the channel CH3 migrate. Furthermore, if the thermal treatment process is performed at 800° C. or lower in order to prevent the migration, impurities are not sufficiently activated.
Third, if it is difficult to dope impurities of a high concentration into the channels CH3, GIDL may be generated by supplying a high voltage to the bit line BL or the source line SL. However, if voltage of 5 V or higher is supplied to the bit line BL or the source line SL, reliability of the memory device is degraded because a junction breakdown phenomenon occurs.
Fourth, in the memory device having the structure shown in FIG. 2B, the contact area of the channel and the bit line BL or the source line SL is narrow because the first and the second select transistors ST1 and ST2 have the channels CH3 that form trenches. Here, characteristics of the memory device are degraded because current is reduced due to increased contact resistance.
Consequently, the generation of holes due to GIDL is difficult in the structure of the conventional U-shaped channel-type non-volatile memory device. Accordingly, an erase error is generated and characteristics of the memory device are degraded.
FIGS. 3A and 3B are graphs showing the program/erase characteristics of the conventional U-shaped channel-type non-volatile memory device. The graph of FIG. 3A relates to the non-volatile memory device having the partial-trench structure described with reference to FIG. 2A, and the graph of FIG. 3B relates to the non-volatile memory device having the full trench structure described with reference to FIG. 2B. The X axis in each graph indicates a voltage, and the Y axis in each graph indicates a current. Furthermore, INI shows the reset state of the memory cell.
From the graphs, it can be seen that current does not rise even if a negative voltage is supplied to the gate electrode of the select transistor. That is, in the conventional structures, an erase error is generated because GIDL is not sufficiently generated in an erase operation. Furthermore, it can be seen that a junction breakdown occurs if voltage is raised in order to generate GIDL.
In particular, it can be seen that the non-volatile memory device having the full trench structure has poor erase characteristics because the channel area into which impurities will be doped and contact resistance is high.